The invention is a timing recovery circuit that is more particularly described as a combination of a phase-locked loop and a frequency-locked loop.
Phase-locked loops are commonly used in arrangements to recover timing information in digital transmission systems. A phase-locked loop includes a detector for measuring the difference between the phase of an incoming signal and the phase of an output signal of a controlled oscillator.
Important design objectives for any phase-locked timing recovery arrangement generally include the realization of narrow jitter bandwidth, well controlled jitter transient response and stable phase offset together with rapid wide range acquisition of the input phase and frequency. Timing recovery circuits for random digital data systems must be designed to recover timing from a timing component which varies statistically in both phase and amplitude.
Phase-locked loop arrangements described in the prior art make compromises among the aforementioned important design objectives. In particular, rapid wide range acquisition is often traded off for improvements in the other objectives. Also, improvement of jitter filtering generally is achieved by some trade off which reduces acquisition range and speed.